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Performance Evaluation of Fully Depleted Silicon on Insulator MOSFET
Yogendra Kumar Sharma, Imran Ullah Khan
Yogendra Kumar Sharma, Imran Ullah Khan, “Performance Evaluation of Fully Depleted Silicon on Insulator MOSFET”, International Journal of Engineering and Applied Computer Science, vol. 04, no. 04, pp. 29-35, May. 2022.
VLSI technology development nowadays is mostly focused on the downsizing of semiconductor devices, which is significantly reliant on advancements in complementary metal-oxide-semiconductor technology. Due to capacitance, shorter channel length, body biassing, faster-switching transistor, limited variability, and faster running transistor, Silicon-on-Insulator technology has seen a lot of changes. In comparison to traditional bulk technology, Silicon on Insulator offers intriguing new possibilities. The recent stalling of advancement in CMOS technology has been noticed. A fully depleted silicon on the insulator provides additional performance. Power usage and communication speed are two areas where performance can be improved. Silicon on insulator technology has the potential to reduce power consumption by nearly half while increasing speed by about 40%. Using the Atlas module of the SILVACO software, the research presents a comprehensive analysis of silicon on insulator-based nano metal oxide semiconductor field-effect transistors. Atlas is used to virtually construct a 20 nm silicon on insulator MOSFET. The gate metals employed are Aluminum, N. poly, W (Tungsten), and WSi2 (Tungsten Silicide), and their respective characteristics are obtained and compared. Finally, WSi2 was chosen as the final gate metal because it has the desired band offset, resulting in a positive threshold voltage without the need for any further implants in the channel region. Other metrics are collected, such as the variation of ID vs. VGS features at various values. There is also a fluctuation in drain current as a function of drain to source voltage.
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